Active matrix flat-panel imagers (AMFPIs) have gained considerable significance in digital imaging, and more recently in diagnostic medical imaging applications, in view of their large area readout capability. The pixel, forming the fundamental unit of the active matrix, comprises a detector and readout circuit to efficiently transfer the collected electrons to external electronics for data acquisition. The pixel architecture most commonly used for large area x-ray imaging is the passive pixel sensor (PPS) shown in FIG. 1a. Here, a detector, for example, an amorphous selenium (a-Se) based photoconductor or a Cesium Iodide (CsI) phosphor coupled to an amorphous silicon (a-Si:H) p-i-n photodiode, is integrated with a readout circuit comprising an a-Si:H thin-film transistor (TFT) switch. Signal charge is accumulated on the pixel capacitance during an integration cycle and is transferred to an external charge amplifier via the TFT switch during a readout/reset cycle. This capacitance is the p-i-n photodiode capacitance or an integrated storage capacitor for the a-Se photoconductor arrangement. FIG. 1b shows a timing diagram for one sequence of operation of a PPS pixel. Cycle 110 and 120 represent the integration cycle and readout/reset cycle, respectively. Other sequences are possible, for example, where double sampling mechanisms are introduced, wherein, double sampling mechanisms are typically used to correct for the effect of non-uniformities within the circuitry. These non-uniformities may comprise process non-uniformities in the form of offsets, and, in the case of a-Si:H technology, non-uniformities in pixel circuit performance due to transistor instability. For example, International Publication Nos. WO9634416 and WO9705659 further disclose flat-panel detectors for radiation imaging using a PPS architecture.
While the PPS has the advantage of being compact and thus amenable to high-resolution imaging, reading a small output signal of the PPS for low input, real-time, large area applications, such as low dose fluoroscopy, requires high performance charge amplifiers. These charge amplifiers can potentially introduce noise that degrades the signal-to-noise ratio (SNR) at low signal levels thus undermining the pixel dynamic range. In particular, fluoroscopy can be one of the most demanding applications for flat-panel imaging systems due to the requirement of real-time readout. Real-time x-ray imaging or fluoroscopy is used in many medical interventional procedures where a catheter is moved through the arterial system under x-ray guidance. The technical challenge to be 10 addressed for these types of fluoroscopy is the need for extremely low noise, or alternatively, an increase in signal size before readout. Studies on a-Si:H PPS pixels suggest that an improvement in SNR of an order of magnitude is desirable in order to apply these systems to more advanced imaging applications.
One approach for improved SNR is disclosed in International Publication No. WO02067337 which discloses that the SNR can be increased by employing in-situ, or pixel, amplification via an a-Si:H current-mediated active pixel sensor (C-APS) as depicted in FIG. 2a. The gain, linearity and noise results reported show an improvement and indicate that the a-Si:H C-APS, coupled together with an established 20 x-ray detection technology such as a-Se or CsI/p-i-n photodiodes, can meet the stringent noise requirements for digital x-ray fluoroscopy, which is less than 1000 electrons of noise.
To perform amplification of a small, noise vulnerable, input signal, such as in fluoroscopy, the C-APS pixel can be used in three operating cycles; a reset cycle, an integration cycle and a readout cycle. FIG. 2b illustrates a timing diagram for a method of operating the C-APS readout circuit employing a double sampling mechanism. In this sequence, during the integration cycle 210, READ transistor 24 and RESET transistor 21 are kept OFF while AMP_RESET transistor 27 is kept ON. Photons incident upon detector 22 result in the generation of electron-hole pairs that discharge, or charge, the capacitance CDETECTOR at node 201 and thus reduce, or increase, the voltage at node 201, VG, by an amount ΔVG. CDETECTOR mainly comprises the detector 22 capacitance and any storage capacitors that may be used.
The readout cycle 220 follows the integration cycle 210 and during this cycle, READ transistor 24 is turned ON, RESET transistor 21 is kept OFF and the AMP_RESET transistor 27 is turned OFF, resulting in a current, IBIAS±ΔIBIAS, that is proportional to VG±ΔVG flowing in the AMP transistor 23 and READ transistor 24 branch. The current, IBIAS±ΔIBIAS is then integrated by charge amplifier 25 to obtain and store an output voltage, VOUT1, on the amplifier feedback capacitor 26.
The reset cycle 230 occurs subsequent to the readout cycle 220 where RESET transistor 21 is pulsed ON and CDETECTOR is charged, or discharged, to reset the voltage at node 201 to VG while RESET transistor 21 is ON. During this reset cycle, READ transistor 24 is turned OFF and AMP_RESET transistor 27 is turned ON.
To perform the double sampling operation, an additional read cycle 240 follows the reset cycle 230 where again READ transistor 24 is turned ON, RESET transistor 21 is turned OFF and AMP_RESET transistor 27 is turned OFF. IBIAS is integrated by charge amplifier 25 to obtain and store an output voltage, VOUT2, on feedback capacitor 26. Subtracting VOUT1 from VOUT2 yields a ΔVOUT that can be free from non-uniformities and is proportional to ΔVG.
ΔIBIAS is proportional to ΔVG and is given as:ΔIBIAS=gmΔVGwhere gm is the transconductance of the AMP transistor 23 and READ transistor 24 readout circuit branch.
The C-APS produces a charge gain, Gi, to amplify the noise vulnerable input signal. The Gi for the C-APS is given as:Gi=(gmTS)/CDETECTORwhere TS is the amount of time IBIAS and ΔIBIAS are integrated on the feedback capacitor 26. As indicated by the equation above, Gi is programmable via gm, TS and the choice of an appropriate CDETECTOR.
A concern with the C-APS circuit is the presence of a small-signal linearity constraint on the x-ray input signal. Using such a pixel amplifier for real-time fluoroscopy, where the exposure level is small, is feasible since the voltage change at the amplifier input is also small and in the order of mV. However, in applications such as digital chest radiography, mammography or higher dose fluoroscopy, the voltage change at the amplifier input can be much larger due to the larger x-ray exposure levels, which cause the C-APS pixel output to be non-linear thus reducing the pixel dynamic range. Another consequence of a non-linear pixel transfer function is that the standard double sampling mechanism cannot be implemented in hardware due to this non-linearity.
Furthermore, an additional shortcoming of the C-APS pixel is that the presence of a large output current, causes the external or off-panel charge amplifier to saturate. Large pixel output currents can also occur when a large charge gain is required since gm is proportional to IBIAS.
Another approach disclosed in International Publication No. WO02067337 reports a near-unity gain pixel amplifier, namely, an a-Si:H voltage-mediated active pixel sensor (V-APS). A V-APS architecture is illustrated in FIG. 3. READ transistor 34, AMP transistor 33 and RESET transistor 31 are components of the V-APS pixel and function in a similar manner as in the C-APS pixel. Resistive load 35 is connected to the pixel output node to convert the current in the AMP transistor 33 and READ transistor 34 branch into an output voltage. Resistive load 35 can comprise a resistor load device or a transistor load device. The input signal voltage VG is translated to a pixel output voltage VOUT with a near unity gain. The V-APS, like the C-APS, can be used in three operating cycles; a reset cycle, an integration cycle and a readout cycle. Like the C-APS, double sampling mechanisms can be applied to the V-APS to correct for the effect of non-uniformities within the circuitry. A problem with the V-APS architecture is that essentially no gain is provided to the input signal. In addition, with current state of the art amorphous silicon technology, it is difficult to achieve real time readout using this architecture when large column bus capacitances are charged and discharged.
Therefore, a pixel design that is able to achieve real-time readout as well as capable of sensing a wider range of input signals is necessary while accounting for large pixel output currents in order to achieve high gain.
This background information is provided for the purpose of making known information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.